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PCF8531
34 x 128 pixel matrix driver
Rev. 04 -- 13 June 2008 Product data sheet
1. General description
The PCF8531 is a low-power CMOS LCD row/column driver, designed to drive dot matrix graphic displays at multiplex rates of 1:17, 1:26 and 1:34. Furthermore, it can drive up to 128 icons. All necessary functions for the display are provided in a single chip, including on-chip generation of VLCD and the LCD bias voltages, resulting in a minimum of external components and low power consumption. The PCF8531 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). All inputs are CMOS compatible. Remark: The icon mode is used to reduce current consumption. When only icons are displayed, a much lower operating voltage (VLCD) can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as VLCD.
2. Features
I I I I I I I I Single-chip LCD controller/driver 34 row and 128 column outputs Display data RAM 34 x 128 bits 128 icons (last row is used for icons) Fast-mode I2C-bus interface (400 kbit/s) Software selectable multiplex rates: 1:17, 1:26 and 1:34 Icon mode with multiplex rate 1:2: N Featuring reduced current consumption while displaying icons only On-chip: N Generation of VLCD (external supply also possible) N Selectable linear temperature compensation N Oscillator requires no external components (external clock also possible) N Generation of intermediate LCD bias voltages N Power-on reset No external components required Software selectable bias configuration Logic supply voltage range VDD1 to VSS1: 1.8 V to 5.5 V Supply voltage range for on-chip voltage generator VDD2 and VDD3 to VSS1 and VSS2: 2.5 V to 4.5 V Display supply voltage range VLCD to VSS: N Normal mode: 4 V to 9 V N Icon mode: 3 V to 9 V Low-power consumption, suitable for battery operated systems
I I I I I
I
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
I CMOS compatible inputs I Manufactured in silicon gate CMOS process
3. Applications
I I I I Telecommunication systems Automotive information systems Point-of-sale terminals Instrumentation
4. Ordering information
Table 1. Ordering information Package Name PCF8531U Description chip with bumps in tray Version Type number
5. Block diagram
R0 to R33 C0 to C127 VDD1 VDD2 VDD3
34
128
VSS1 VSS2 T1 T2 T3 T4
ROW DRIVERS
COLUMN DRIVERS POWER-ON RESET ENR
PCF8531
INTERNAL RESET
RES
DATA LATCHES VLCDIN BIAS VOLTAGE GENERATOR MATRIX LATCHES
OSCILLATOR
OSC
TIMING GENERATOR DISPLAY DATA RAM VLCD GENERATOR MATRIX DATA RAM DISPLAY ADDRESS COUNTER
VLCDSENSE VLCDOUT
SCL SDA SDACK INPUT FILTERS
I2C-BUS CONTROL
COMMAND DECODER
ADDRESS COUNTER
mgs465
SA0
Fig 1.
Block diagram of PCF8531
PCF8531_4
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Product data sheet
Rev. 04 -- 13 June 2008
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NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
6. Pinning information
6.1 Pinning
R0
R32 C0
C31 C32
C63 C64
C95 C96
C127 R33
R1 pad1
The positioning of the bonding pads is not to scale.
Fig 2.
PCF8531_4
Bonding pad location for PCF8531
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T2
SCL T1 T3 VSS1 VSS2 T4 ENR SA0 SDACK 0,0 x y SDA VDD1
VDD2
VDD3 RES VLCDIN VLCDOUT VLCDSENSE OSC
PCF8531
mgs486
3 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
Pad allocation table Symbol OSC VLCDSENSE VLCDOUT VLCDIN RES VDD3 VDD2 VDD1 SDA Pad 55 56 57 to 63 64 to 70 71 72 73 to 74 78 87 to 103 Symbol ENR T4 VSS2 VSS1 T3 T1 SCL T2 R0, R2, R4, R6, R8, R10, R12, R14, R16, R18, R20, R22, R24, R26, R28, R30, R32 C0 to C127 R33, R31, R29, R27, R25, R23, R21, R19, R17, R15, R13, R11, R9, R7, R5, R3, R1
Table 2. Pad 15 16 17 to 23 24 to 30 31 32 to 34 35 to 42 43 to 49 50 to 51
52 54
SDACK SA0
104 to 231 232 to 248
100 m
80 m
y center
100 m
y center
100 m
y center
100 m
x center circle
x center C
x center F
mgs490
Fig 3. Table 3. C1 C2 F Circle 1 Circle 2
Alignment markers Alignment markers for PCF8531 x (m) -5402.0 5292.4 5890.3 -5543.0 5637.4 y (m) 823.1 950.0 401.9 798.4 798.4
Alignment marks
PCF8531_4
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Product data sheet
Rev. 04 -- 13 June 2008
4 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
L
W
PCF8531
pitch Y
X
001aag908
Fig 4. Table 4. Pad Pad pitch
Chip dimensions Bonding pad dimensions Size 70 50 x 90 x 17.5 (3) 381 12.23 x 1.96 12.14 x 1.86 Unit m m m mm mm
Bump dimensions Wafer thickness (excluding bumps) Die size L x W Fab 1[1] Fab
[1] [2]
2[2]
Fab 1 identification starts with nnnnnn, where n represents a number between 0 and 9. Fab 2 identification starts with AXnnnn, where X represents a letter and n represents a number between 0 and 9.
6.2 Pin description
Table 5. Bonding pad description All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). Symbol OSC
PCF8531_4
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
X (m) 5973.6 5969.5 5899.5 5829.5 5479.5 5409.5 5059.5 4989.5 4639.5 4569.5 4219.5 4149.5 3799.5 3729.5 3449.5
Y (m) -821.7 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4
Description dummy
oscillator input
[1]
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Product data sheet
Rev. 04 -- 13 June 2008
5 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
Table 5. Bonding pad description ...continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). Symbol VLCDSENSE VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN RES VDD3 VDD3 VDD3 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 SDA SDA SDACK SA0
PCF8531_4
Pad 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
X (m) 3169.5 3099.5 3029.5 2959.5 2889.5 2819.5 2749.5 2679.5 2539.5 2469.5 2399.5 2329.5 2259.5 2189.5 2119.5 1979.5 1699.5 1629.5 1559.5 1279.5 1209.5 1139.5 1069.5 999.5 929.5 859.5 789.5 649.5 579.5 509.5 439.5 369.5 299.5 229.5 19.5 -50.5 -400.5 -750.5 -820.5
Y (m) 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4
Description voltage multiplier regulation input (VLCD) voltage multiplier output (VLCD)
[2] [3]
LCD supply voltage (VLCD)
[2]
external reset input (active LOW) supply voltage 3
[4] [5]
supply voltage 2
[5]
supply voltage 1
[5]
serial data line input of the I2C-bus serial data acknowledge output dummy I2C-bus slave address input; bit 0
(c) NXP B.V. 2008. All rights reserved.
[6]
Product data sheet
Rev. 04 -- 13 June 2008
6 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
Table 5. Bonding pad description ...continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). Symbol ENR T4 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 T3 T1 SCL SCL T2 R0 R2 R4 R6 R8 R10 Pad 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 X (m) -1100.5 -1380.5 -1660.5 -1730.5 -1800.5 -1870.5 -1940.5 -2010.5 -2080.5 -2220.5 -2290.5 -2360.5 -2430.5 -2500.5 -2570.5 -2640.5 -2780.5 -3060.5 -3410.5 -3480.5 -3830.5 -4180.5 -4530.5 -4600.5 -4880.5 -4950.5 -5230.5 -5300.5 -5650.5 -5720.5 -5930.5 -5926.4 -5786.4 -5716.4 -5646.4 -5576.4 -5506.4 -5436.4 Y (m) 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 823.4 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 LCD row driver output test 2 output dummy
[10]
Description enable internal power-on reset input test input 4 ground 2
[7] [8] [9]
ground 1
[9]
test 3 test 1 serial clock line input of the I2C-bus dummy
[8] [8]
PCF8531_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
7 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
Table 5. Bonding pad description ...continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). Symbol R12 R14 R16 R18 R20 R22 R24 R26 R28 R30 R32 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27
PCF8531_4
Pad 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131
X (m) -5366.4 -5296.4 -5226.4 -5156.4 -5086.4 -5016.4 -4946.4 -4876.4 -4806.4 -4736.4 -4666.4 -4526.4 -4456.4 -4386.4 -4316.4 -4246.4 -4176.4 -4106.4 -4036.4 -3966.4 -3896.4 -3826.4 -3756.4 -3688.4 -3616.4 -3546.4 -3476.4 -3406.4 -3336.4 -3266.4 -3196.4 -3126.4 -3056.4 -2986.4 -2916.4 -2846.4 -2776.4 -2706.4 -2636.4
Y (m) -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7
Description LCD row driver output
LCD column driver output
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Product data sheet
Rev. 04 -- 13 June 2008
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NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
Table 5. Bonding pad description ...continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). Symbol C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66
PCF8531_4
Pad 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170
X (m) -2566.4 -2496.4 -2426.4 -2356.4 -2216.4 -2146.4 -2076.4 -2006.4 -1936.4 -1866.4 -1796.4 -1726.4 -1656.4 -1586.4 -1516.4 -1446.4 -1376.4 -1306.4 -1236.4 -1166.4 -1096.4 -1026.4 -956.4 -886.4 -816.4 -746.4 -676.4 -606.4 -534.6 -466.4 -396.4 -326.4 -256.4 -186.4 -116.6 -46.4 93.6 163.6 233.6
Y (m) -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7
Description LCD column driver output
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Product data sheet
Rev. 04 -- 13 June 2008
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NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
Table 5. Bonding pad description ...continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). Symbol C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103 C104 C105
PCF8531_4
Pad 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209
X (m) 303.6 373.3 443.6 513.6 583.6 653.6 723.6 793.6 863.6 933.6 1003.6 1073.6 1143.6 1213.6 1283.6 1353.6 1423.6 1493.6 1563.6 1633.6 1703.6 1773.6 1843.6 1913.6 1983.6 2053.6 2123.6 2193.6 2263.6 2403.6 2473.6 2543.6 2613.6 2683.6 2753.6 2823.6 2893.6 2963.6 3033.6
Y (m) -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7
Description LCD column driver output
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Product data sheet
Rev. 04 -- 13 June 2008
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NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
Table 5. Bonding pad description ...continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 2). Symbol C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 R33 R31 R29 R27 R25 R23 R21 R19 R17 R15 R13 R11 R9 R7 R5 R3 R1
PCF8531_4
Pad 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248
X (m) 3103.6 3173.6 3243.6 3313.6 3383.6 3453.6 3523.6 3593.6 3663.6 3733.6 3803.6 3873.6 3943.6 4013.6 4083.6 4153.6 4223.6 4293.6 4363.6 4433.6 4503.6 4573.6 4713.6 4783.6 4853.6 4923.6 4993.6 5063.6 5113.6 5203.6 5343.6 5413.6 5483.6 5553.6 5623.6 5693.6 5763.6 5833.6 5903.6
Y (m) -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7 -821.7
Description LCD column driver output
LCD row driver output; icon row LCD row driver output
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Product data sheet
Rev. 04 -- 13 June 2008
11 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
[1] [2] [3] [4] [5]
If the on-chip oscillator is used, this input must be connected to VDD1. If the internal VLCD generation is used, VLCDOUT, VLCDIN and VLCDSENSE must be connected together. If an external VLCD is used in the application, then pin VLCDOUT must be left open-circuit, otherwise the chip will be damaged. If only the internal power-on reset is used, this input must be connected to VDD1. VDD1 is for the logic supply, VDD2 and VDD3 are for the voltage multiplier. For split power supplies, VDD2 and VDD3 must be connected together. If only one supply voltage is available, VDD1, VDD2 and VDD3 must be connected together. Serial data acknowledge for the I2C-bus. By connecting SDACK to SDA externally, the SDA line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDACK pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that the PCF8531 will not be able to create a valid logic 0 level during the acknowledge cycle. By splitting the SDA input from the SDACK output, the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level. If ENR is connected to VSS, power-on reset is disabled; to enable power-on reset ENR must be connected to VDD1. In the application, this input must be connected to VSS. VSS1 and VSS2 must be connected together.
[6]
[7] [8] [9]
[10] In the application, T2 must be left open-circuit.
PCF8531_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
12 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
7. Functional description
7.1 Oscillator
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD. An external clock signal, if used, is connected to this input.
7.2 Power-on reset
The on-chip power-on reset initializes the chip after power-on or power failure.
7.3 I2C-bus controller
The I2C-bus controller receives and executes the commands. The PCF8531 acts as an I2C-bus slave receiver and therefore it cannot control bus communication.
7.4 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.
7.5 Display data RAM
The PCF8531 contains 34 x 128 bits static RAM for storing the display data, see Figure 7. The RAM is divided into 6 banks of 128 bytes (6 x 8 x 128 bits). Bank 5 is used for icon data. During RAM access, data is transferred to the RAM via the I2C-bus interface. There is a direct correspondence between the X address and column output number.
7.6 Timing generator
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data buses.
7.7 Address counter
The address counter sets the addresses of the display data RAM for writing.
7.8 Display address counter
The display address counter generates the addresses for read out of the display data.
7.9 Command decoder
The command decoder identifies command words that arrive on the I2C-bus and determines the destination for the following data bytes.
7.10 Bias voltage generator
The bias voltage generator generates four buffered intermediate bias voltages. This block contains the generator for the reference voltages and the four buffers. This block can operate in two voltage ranges:
* Normal mode: 4.0 V to 9.0 V
PCF8531_4 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
13 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
* Power save mode: 3.0 V to 9.0 V. 7.11 VLCD generator
The VLCD voltage generator contains a configurable 2 to 5 times voltage multiplier; this is programmed by software.
7.12 Reset
The PCF8531 has the possibility of two reset modes: internal power-on reset or external reset (RES). The reset mode is selected using the ENR signal. After a reset, the chip has the following state:
* All row and column outputs are set to VSS (display off) * RAM data is undefined * Power-down mode 7.13 Power-down
During power-down, all static currents are switched off (no internal oscillator, no timing and no LCD segment drive system) and all LCD outputs are internally connected to VSS. The I2C-bus function remains operational.
7.14 Column driver outputs
The LCD drive section includes 128 column outputs (C0 to C127) which must be connected directly to the LCD. The column output signals are generated in accordance with the multiplexed row signals and with the data in the display latch. When less than 128 columns are required, the unused column outputs must be left open-circuit.
7.15 Row driver outputs
The LCD drive section includes 34 row outputs (R0 to R33), which must be connected directly to the LCD. The row output signals are generated in accordance with the selected LCD drive mode. If less than 34 rows or lower multiplex rates are required, the unused outputs must be left open-circuit. The row signals are interlaced i.e. the selection order is R0, R2, ..., R1, R3, etc.
PCF8531_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
14 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
8. LCD waveforms and DDRAM to data mapping
The LCD waveforms and the DDRAM to display data mapping are shown in Figure 5, Figure 6 and Figure 7.
frame n
frame n + 1 Vstate1(t) Vstate2(t)
ROW 0 R0(t)
VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS
ROW 1 R1(t)
COL 0 C0(t)
COL 1 C1(t)
VLCD V3 - VSS VLCD - V2 0V V3 - V2 V4 - V5 0V VSS - V5 V4 - VLCD -VLCD VLCD V3 - VSS VLCD - V2 0V V3 - V2 V4 - V5 0V VSS - V5 V4 - VLCD -VLCD
Vstate1(t)
Vstate2(t)
0 2 4 6 8...
... 32 1 3 5 7...
... 33 0 2 4 6 8...
... 32 1 3 5 7...
... 33
mgs466
(1) Vstate1(t) = C1(t) - R0(t) (2) Vstate2(t) = C1(t) - R1(t)
Fig 5.
Typical LCD driver waveforms
PCF8531_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
15 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
frame n
frame n + 1 only icons are driven
VLCD V2 V3
ROW 0 to 32
V4 V5 VSS VLCD V2 V3
ROW 33
V4 V5 VSS VLCD V2 V3
COL 1 on/off
V4 V5 VSS VLCD V2 V3
COL 2 off/on
V4 V5 VSS VLCD V2 V3
COL 3 on/on
V4 V5 VSS VLCD V2 V3
COL 4 off/off
V4 V5 VSS
mgs467
Fig 6.
Icon mode; multiplex rate 1:2 LCD waveforms
PCF8531_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
16 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
DDRAM
bank 0 top of LCD R0
bank 1
R8
bank 2
R16
LCD
bank 3
R24
bank 4
R32 R33 (icon row)
bank 5
mgs468
Fig 7.
DDRAM to display data mapping
8.1 Addressing
Data is written in bytes into the RAM matrix of the PCF8531 as shown in Figure 8, Figure 9 and Figure 10. The display RAM has a matrix of 34 x 128 bits. The columns are addressed by the address pointer. The address ranges are X 0 to X 127 (7Fh) and Y 0 to Y 5 (5h). Addresses outside of these ranges are not allowed. In vertical addressing mode (V = 1), the Y address increments after each byte (see Figure 9). After the last Y address (Y = 4), Y wraps around to 0 and X increments to address the next column. In horizontal addressing mode (V = 0), the X address increments after each byte (see Figure 10). After the last X address (X = 127), X wraps around to 0 and Y increments to address the next
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34 x 128 pixel matrix driver
row. After the very last address (X = 127 and Y = 4), the address pointers wrap around to address (X = 0 and Y = 0). The Y address 5 is reserved for icon data and is not affected by the addressing mode. Please note that in bank 4 only the LSB (DB0) of the data is written into the RAM and in bank 5 only the 5th data bit (DB4) is written into the RAM.
LSB
0 MSB LSB 1 2 Y address 3 MSB LSB 0 MSB icon data X address 127 4 5
mgs469
Fig 8.
RAM format and addressing
0 1 2 3 4 0
5 6
0 1 2 638 639 Y address 3 4 5
1
icon data
0
X address
127
mgs470
Fig 9.
Sequence of writing data bytes into RAM with vertical addressing (V = 1)
0 128 256 384 512 0
1 129 257 385 513 1
2 130 258 386 514 icon data
127 255 383 511 639
0 1 2 3 4 5 Y address
0
X address
127
mgs471
Fig 10. Sequence of writing data bytes into RAM with horizontal addressing (V = 0)
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9. Instructions
Only two PCF8531 registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the MPU. Before internal operation, control information is stored temporarily in these registers to allow interfacing to various types of MPUs which operate at different speeds or to allow interfacing to peripheral control ICs. The PCF8531 operation is controlled by the instructions given in Table 11. Instructions are of four types:
* * * *
Those that define PCF8531 functions e.g. display configuration, etc. Those that set internal RAM addresses Those that perform data transfer to/from the internal RAM Others
In normal mode instructions which perform data transfer to/from the internal RAM are used most frequently. Automatic incrementing by 1 of internal RAM addresses after each data write reduces the MPU program load.
9.1 Reset
After reset or internal power-on reset (depending on the application), the LCD driver is set to the following state:
* * * * * * * * * * *
Power-down mode (PD = 1) Horizontal addressing (V = 0) Display blank (D = 0; E = 0), no icon mode (IM = 0) Address counter X[6:0] = 0; Y[2:0] = 0 Bias system BS[2:0] = 0 Multiplex rate M[1:0] = 0 (multiplex rate 1:17) Temperature control mode TC[2:0] = 0 HV-gen control, HVE = 0 the HV generator is switched off, PRS = 0 and S[1:0] = 0 VLCD = 0 V RAM data is undefined Command page definition H[1:0] = 0
9.2 Function set
9.2.1 PD
When PD = 1, the Power-down mode of the LCD driver is active:
* * * * *
PCF8531_4
All LCD outputs at VSS (display off) Power-on reset detection active, oscillator off VLCD can be disconnected I2C-bus is operational, commands can be executed RAM contents not cleared; RAM data can be written
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* Register settings remain unchanged
9.2.2 V
When V = 0 the horizontal addressing is selected. The data is written into the DDRAM as shown in Figure 10. When V = 1 the vertical addressing is selected. The data is written into the DDRAM as shown in Figure 9. Icon data is written independently of V when Y address is 5.
9.3 Set Y address
Bits Y2, Y1 and Y0 define the Y address vector of the display RAM (see Table 6).
Table 6. Y2 0 0 0 0 1 1 Y address Y1 0 0 1 1 0 0 Y0 0 1 0 1 0 1 Bank 0 1 2 3 4 5 (icons)
9.4 Set X address
The X address points to the columns. The range of X is 0 to 127 (7Fh).
9.5 Set multiplex rate
M[1:0] selects the multiplex rate (see Table 7).
Table 7. 1:17 1:26 1:34 Multiplex rates M1 0 1 0 M0 0 0 1
Multiplex rate
9.6 Display control (D, E and IM)
Bits D and E select the display mode (see Table 13). Bit IM (see Table 12) sets the display to icon mode.
9.7 Set bias system
Different multiplex rates require different bias settings. Bias settings are programmed by BS[2:0], which sets the binary number n. The optimum value for n is given by: n= muxrate - 3
Supported values of n are given in Table 8. Table 9 shows the intermediate bias voltages.
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Programming the required bias system BS1 0 0 1 1 0 0 1 1 BS0 0 1 0 1 0 1 0 1 n 7 6 5 4 3 2 1 0 Bias system
1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4
Table 8. BS2 0 0 0 0 1 1 1 1
Comment
recommended for 1:34 recommended for 1:26 recommended for 1:17 recommended for icon mode
9.8 LCD bias voltage
Table 9. Symbol V1 V2 V3 V4 V5 V6 Intermediate LCD bias voltages Bias voltage VLCD n+3 ----------- x V LCD n+4 n+2 ----------- x V LCD n+4 2 ----------- x V LCD n+4 1 ----------- x V LCD n+4 VSS Example for 17 bias VLCD
6 7
x VLCD x VLCD x VLCD x VLCD
5
7
2
7
1
7
VSS
9.9 Set VLCD value
VLCD can be set by software. The voltage at intersection temperature [VLCD (T = Tints)] can be calculated as: VLCD (Tints) = a + VLCD x b The generated voltage is dependent on the temperature, programmed Temperature Coefficient (TC) and the programmed voltage at intersection temperature (Tints). VLCD = VLCD (Tints) x [1 + TC x (T - Tints)] The parameter values are given in Table 10. Two overlapping VLCD ranges can be selected via the command `HV-gen control' (see Table 10 and Figure 11). The maximum voltage which can be generated depends on the VDD2 and VDD3 voltages and the display load current. For multiplex rate 1:34, the optimum VLCD can be calculated as: 1 + 34 V LCD = ------------------------------------- x V th = 5.30 x V th 1 2 x 1 - --------- 34 Where Vth is the threshold voltage of the liquid crystal material used.
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The practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user must ensure, while setting the VOP register and selecting the temperature compensation, that the VLCD limit maximum of 9.0 V is never exceeded under all conditions and including all tolerances.
Table 10. Symbol Tints a b Programming range Parameter values for the HV generator programming Value PRS = 0 27 2.94 0.03 2.94 to 6.75 PRS = 1 27 6.75 0.03 6.75 to 10.56 C V V V Unit
VLCD
b
a
00
01
02
03
04
05 LOW
06
. . . 7D 7E
7F
00
01
02
03
04
05 HIGH
06
. . . 5F
6F
7F
mgl935
VOP[6:0] (programmed) [00h to 7Fh] program range LOW to HIGH
Fig 11. VLCD programming of PCF8531
9.10 Voltage multiplier control S[1:0]
The PCF8531 incorporates a software configurable voltage multiplier. After reset (internal or external), the voltage multiplier is set to 2 x VDD2. The voltage multiplier factors are set by setting bits S[1:0] (see Table 13).
9.11 Temperature compensation
Due to the temperature dependency of the liquid crystal's viscosity, the LCD controlling voltage VLCD should usually be increased at lower temperatures to maintain optimum contrast. Figure 12 shows VLCD for high multiplex rates.
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34 x 128 pixel matrix driver
mgs473
VLCD
0 C
T
Fig 12. VLCD as a function of liquid crystal temperature
Linear temperature compensation is supported in the PCF8531. The temperature coefficient of VLCD can be selected from eight values by setting bits TC[2:0] (see Table 13).
Table 11. Instruction set I2C-bus command[1] RS NOP Write data Set default H[1:0] Instruction set Function set 0 1 0 0 0 R/W 0 0 0 0 0 I2C-bus command byte DB7 0 D7 0 0 0 DB6 0 D6 0 0 0 DB5 0 D5 0 0 1 DB4 0 D4 0 0 0 DB3 0 D3 0 1 0 DB2 0 D2 0 0 PD DB1 0 D1 0 H1 V DB0 0 D0 1 H0 0 no operation write data to display RAM select H[1:0] = 0 select command page power-down control; entry mode Set Y address of RAM; 0 Y 5 Set X address of RAM; 0 X 127 Description
Instruction
H1 and H0 = don't care (H independent command page)
H1 = 0 and H0 = 0 (function and RAM command page)
Set Y address of RAM Set X address of RAM Multiplex rate Display control Bias system HV-gen control HV-gen configuration Test modes VLCD control
[1]
0 0
0 0
0 1
1 X6
0 X5
0 X4
0 X3
Y2 X2
Y1 X1
Y0 X0
H1 = 0 and H0 = 0 (display setting command page) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 X 0 0 1 0 0 0 X 0 1 0 0 1 0 X 1 D BS2 1 0 TC2 X M1 IM BS1 PRS S1 TC1 X M0 E BS0 HVE S0 TC0 X
H1 = 0 and H0 = 0 (HV-gen command page)
Temperature control 0 0 0
VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0
R/W is set to the slave address byte; Co and RS are set in the control byte.
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Explanation for symbols in Table 11 0 chip is active horizontal addressing normal mode; full display + icons
[1]
Table 12. Bit PD V IM H[1:0] D and E HVE PRS TC[2:0] S[1:0]
[1]
1 chip is in Power-down mode vertical addressing icon mode; only icons are displayed
see Table 13 see Table 13 voltage multiplier disabled VLCD programming range LOW see Table 13 see Table 13 voltage multiplier enabled VLCD programming range HIGH
The bits H[1:0] identify the command page (use `Set default H[1:0]' command to set H[1:0] = 0).
Table 13. Bits
Description of bits H, D and E, TC and S Value 00 01 10 Description function and RAM command page display setting command page HV-gen command page display blank normal mode all display segments inverse video mode temperature coefficient TC0 temperature coefficient TC1 temperature coefficient TC2 temperature coefficient TC3 temperature coefficient TC4 temperature coefficient TC5 temperature coefficient TC6 temperature coefficient TC7 2 x voltage multiplier 3 x voltage multiplier 4 x voltage multiplier 5 x voltage multiplier
Command page (H) H[1:0]
Display modes (D, E) D and E 00 10 01 11 Temperature coefficient (TC) TC[2:0] 000 001 010 011 100 101 110 111 Voltage multiplier factor (S) S[1:0] 00 01 10 11
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10. Internal circuitry
PADS 43 to 49 VDD1 PADS 35 to 42 VDD2 PADS 32 to 34
VDD3
VSS1
VSS1 VSS2
VSS1
PADS 64 to 70
PADS 57 to 63
PADS 57 to 63
VSS2
PADS 16, 24 to 30
VLCDIN (SUPPLY), VLCDSENSE
PADS 17 to 23
VLCDOUT
VSS1
VSS1
VSS1
VDD1
VLCDIN
PADS 73, 74, 50, 51, 52
SCL, SDA, SDACK
PADS 87 to 248
VSS1
VSS1
VDD1
VDD1
PADS 15, 54, 71, 72, 56, 31, 55
OSC, SA0, T3, T1, T4, RES, ENR
PAD 78
T2
VSS1
VSS1
mgs485
For all diagrams the maximum forward current is 5 mA and the maximum reverse voltage is 5 V.
Fig 13. Device protection diagrams
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11. I2C-bus interface
11.1 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
11.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 14).
SDA
SCL data line stable; data valid change of data allowed
mbc621
Fig 14. Bit transfer
11.1.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are shown in Figure 15.
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 15. Definition of START and STOP conditions
11.1.3 System configuration
The system configuration is shown in Figure 16.
* Transmitter: the device that sends the data to the bus * Receiver: the device that receives the data from the bus * Master: the device that initiates a transfer, generates clock signals and terminates a
transfer
* Slave: the device addressed by a master
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* Multi-master: more than one master can attempt to control the bus at the same time
without corrupting the message
* Arbitration: procedure to ensure that, if more than one master simultaneously tries to
control the bus, only one is allowed to do so and the message is not corrupted
* Synchronization: procedure to synchronize the clock signals of two or more devices.
MASTER TRANSMITTER/ RECEIVER SDA SCL
mga807
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
Fig 16. System configuration
11.1.4 Acknowledge
Acknowledge on the I2C-bus is shown in Figure 17. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter, during which time the master generates an extra acknowledge related clock pulse. A slave receiver addressed must generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an "end of data" to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 17. Acknowledge on the I2C-bus
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11.2 I2C-bus protocol
This driver does not support `read'. The PCF8531 is a slave receiver. Therefore, it only responds when R/W = 0 in the slave address byte. Before any data is transmitted on the I2C-bus, the device that must respond is addressed first. Two 7-bit slave addresses (011 1100 and 011 1101) are reserved for the PCF8531. The least significant bit of the slave address is set by connecting the input SA0 to either logic 0 (VSS) or logic 1 (VDD). The I2C-bus protocol is shown in Figure 18. The sequence is initiated with a START condition (S) from the I2C-bus master, and is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all others ignore the I2C-bus transfer. After acknowledgement, one or more command words follow, which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and RS, plus a data byte (see Figure 19 and Table 11). The last control byte is tagged with a cleared most significant bit, the continuation bit Co. The control and data bytes are also acknowledged by all addressed slaves on the bus. After the last control byte, depending on the RS bit setting, either a series of display data bytes or command data bytes may follow. If the RS bit was set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended PCF8531 device. If the RS bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed PCF8531. At the end of the transmission, the I2C-bus master issues a STOP condition (P).
slave address S 0 1 1 1 1 0 SA0 R/W A Co RS X
control byte X X X X X
mgs474
Fig 18. Slave address and control byte
acknowledge from PCF8531 S S 0 1 1 1 1 0 A 0 A 1 RS 0 slave address
acknowledge from PCF8531
acknowledge from PCF8531
acknowledge from PCF8531
acknowledge from PCF8531
control byte
A
data byte
A 0 RS
control byte
A
data byte n 0 bytes MSB . . . . . . . . . . . LSB
AP
R/W Co
2n 0 bytes
Co
1 byte
mgs475
Fig 19. Master transmits to slave receiver; write mode
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11.3 Command decoder
The command decoder identifies command words that arrive on the I2C-bus. The most significant bit of a control byte is the continuation bit Co. If this bit is logic 1, it indicates that only one data byte (either command or RAM data) will follow. If this bit is logic 0, it indicates that a series of data bytes (either command or RAM data) may follow. The DB6 bit of a control byte is the RAM data/command bit RS. When this bit is at logic 1, it indicates that another RAM data byte will be transferred next. If the bit is at logic 0, it indicates that another command byte will be transferred next.
* Pairs of bytes; information in the second byte, the first byte determines whether
information is display or instruction data
* Stream of information bytes after Co = 0; display or instruction data, depending on
last RS (Register Selection).
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12. Limiting values
Table 14. Limiting values [1] In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD1 VDD2 VDD3 VLCD VI VO IDD(LCD) ISS II IO Ilu Ptot P/out Vesd Parameter supply voltage 1 supply voltage 2 supply voltage 3 LCD supply voltage input voltage output voltage LCD supply current ground supply current input current output current latch-up current total power dissipation power dissipation per output electrostatic discharge voltage HBM MM CDM Tj Tstg
[1] [2] [3] [4] [5]
[3] [4] [5] [2]
Conditions logic supply multiplier supply multiplier supply
Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -50 -50 -10 -10 -65
Max +5.5 +4.5 +4.5 +9.0 VDD + 0.5 VDD + 0.5 +50 +50 +10 +10 100 300 30 2000 200 2000 +150 +150
Unit V V V V V V mA mA mA mA mA mW mW V V V C C
junction temperature storage temperature
Parameters are valid over the whole operating temperature range unless otherwise specified. All voltages are referenced to VSS unless otherwise specified. Latch-up testing, according to JESD78. HBM: Human Body Model, according to JESD22-A114. MM: Machine Model, according to JESD22-A115. CDM: Charged Device Model, according to JESD22-C101.
13. Static characteristics
Table 15. Static characteristics VDD1 = 1.8 V (1.9 V) to 5.5 V; VDD2 and VDD3 = 2.5 V to 4.5 V; VSS1 = VSS2 = 0 V; VDD1 to VDD3 VLCD 9.0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VLCD VDD1 VDD2 VDD3
PCF8531_4
Parameter LCD supply voltage
Conditions
[1]
Min 4.0 3.0 1.9 1.8 2.5 2.5
Typ -
Max 9.0 9.0 5.5 5.5 4.5 4.5
Unit V V V V V V
icon mode supply voltage 1 supply voltage 2 supply voltage 3 logic supply Tamb -25 C multiplier supply; LCD voltage internally generated multiplier supply; LCD voltage internally generated
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[1]
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Table 15. Static characteristics ...continued VDD1 = 1.8 V (1.9 V) to 5.5 V; VDD2 and VDD3 = 2.5 V to 4.5 V; VSS1 = VSS2 = 0 V; VDD1 to VDD3 VLCD 9.0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol IDD Parameter supply current Conditions Power-down mode; internal VLCD normal mode; internal VLCD normal mode; external VLCD IDD(LCD) VPOR Logic VIL VIH IOL(SDA) ILI RO Vbias VLCD TC LOW-level input voltage HIGH-level input voltage LOW-level output current on pin SDA input leakage current output resistance bias voltage variation LCD voltage variation temperature coefficient VOL = 0.4 V; VDD = 5.0 V VI = VDD or VSS column outputs: C0 to C127 row outputs: R0 to R33 outputs R0 to R33 and C0 to C127 TC1 to TC7 Tamb = -20 C to +70 C TC0; TC[2:0] = 000 TC1; TC[2:0] = 001 TC2; TC[2:0] = 010 TC3; TC[2:0] = 011 TC4; TC[2:0] = 100 TC5; TC[2:0] = 101 TC6; TC[2:0] = 110 TC7; TC[2:0] = 111 Tints
[1]
[8] [7] [2][3] [2] [2][4] [2][5] [6]
Min 0.9 VSS 0.7VDD 3.0 -1 -100 -
Typ 2 170 10 25 15 1.2 12 12 0 0 -0.026 -0.039 -0.052 -0.078 -0.13 -0.19 -0.26 27
Max 10 350 50 100 70 1.6 0.3VDD VDD +1 20 20 +100 3.9 -
Unit A A A A A V V V mA A k k mV % %/K %/K %/K %/K %/K %/K %/K %/K C
LCD supply current power-on reset voltage
normal mode; external VLCD icon mode; external VLCD
Column and row outputs
intersection temperature
As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user must ensure, while setting the VOP register and selecting the temperature compensation, that the VLCD maximum limit of 9 V will never be exceeded under all conditions and including all tolerances. LCD outputs are open circuit, inputs at VDD or VSS; bus inactive. VDD1 to VDD3 = 2.85 V; VLCD = 7.0 V; voltage multiplier = 3 x VDD; fosc = 34 kHz. VDD1 to VDD3 = 2.75 V; VLCD = 9.0 V; fosc = 34 kHz. VDD1 to VDD3 = 2.75 V; VLCD = 3.5 V; fosc = 34 kHz. Resets all logic when VDD1 < VPOR. Iload 50 A; outputs are tested one at a time. VLCD 7.7 V.
[2] [3] [4] [5] [6] [7] [8]
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14. Dynamic characteristics
Table 16. Dynamic characteristics VDD1 = 1.8 V (1.9 V) to 5.5 V; VDD2 and VDD3 = 2.5 V to 4.5 V; VSS1 = VSS2 = 0 V; VDD1 to VDD3 VLCD 9.0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ffr(LCD) fosc fclk(ext) tw(RESL) tsu(RESL) fSCL tLOW tHIGH tSU;DAT tHD;DAT tr tf Cb tSU;STA tHD;STA tSU;STO tSP tBUF Parameter LCD frame frequency oscillator frequency external clock frequency RES LOW pulse width RES LOW set-up time SCL clock frequency LOW period of the SCL clock HIGH period of the SCL clock data set-up time data hold time rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line set-up time for a repeated START condition hold time (repeated) START condition set-up time for STOP condition pulse width of spikes that must be suppressed by the input filter bus free time between a STOP and START condition
ffr = fclk(ext)/480 or fosc/480. A reset is generated if tw(RESL) > 3 ns (see Figure 20). All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH, with an input voltage swing of VSS to VDD. Cb = total capacitance of one bus line in pF.
[4] [4] [2]
Conditions VDD = 3.0 V
[1]
Min 40 20 20 300 0 1.3 0.6 100 0
Typ 66 34 -
Max 135 65 65 30 400 0.9 0.3 0.3 400 50 -
Unit Hz kHz kHz ns s kHz s s ns ns s s pF s s s ns s
Serial bus interface (see Figure 21)[3]
20 + 0.1Cb 20 + 0.1Cb 0.6 0.6 0.6 -
on bus
1.3
[1] [2] [3] [4]
VDD
RES
VIL tsu(RESL) tw(RESL)
mgs476
Fig 20. Reset timing
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SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA tSU;STO
mga728
Fig 21. I2C-bus timing
400 IDD (A) 300
mgs477
400 IDD (A) 300
mgs478
2x 5x 4x 3x
200
VLCD = 9 V 7.5 V 4V
200
100
2
3
4 5 VDD2 and VDD3 (V)
100
2
4
6
8 VLCD (V)
10
VDD1 = 2 V; 4 x voltage multiplier; Tamb = 27 C; TC = 0; BS = 100; no VLCD load.
VDD1 = 1.8 V; VDD2 and VDD3 = 2.6 V; Tamb = 27 C; fosc = 34 kHz; no VLCD load.
Fig 22. Supply current as a function of supply voltage 2 and supply voltage 3
Fig 23. Supply current as a function of LCD supply voltage; different multiplication factors
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NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
9 VLCD (V) 8
mgs479
30 I (A) 20
mgs480
IDD(LCD)
TC0 TC1 7 TC6 TC7 10
IDD
6 -50
0 0 50 T (C) 100 2 4 6 8 VLCD (V) 10
VLCD = 7.5 V; VDD1 to VDD3 = 2.7 V; Tamb = 27 C; no VLCD load.
VDD1 = 1.8 V; VDD2 and VDD3 = 2.5 V; external VLCD; Tamb = 27 C; TC = 0; BS = 100; no VLCD load.
Fig 24. LCD supply voltage as a function of temperature
Fig 25. Supply current as a function of LCD supply voltage
30 I (A) 20 I DD(LCD)
mgs481
86 I DD (A) 84
mgs482
82
10 I DD 80
0 0 20 40 60 f (kHz) 80
78 3 3.2 3.4 3.6 4 3.8 VLCD (V)
VDD1 = 2.5 V; VDD2 and VDD3 = 2.5 V; external VLCD; Tamb = 27 C; TC = 0; BS = 100; no VLCD load.
VDD1 = 1.8 V; VDD2 = 2.5 V; 2 x voltage multiplier; Tamb = 27 C; TC = 0; BS = 111; no VLCD load.
Fig 26. Supply current as a function of frequency
Fig 27. Supply current as a function of LCD supply voltage
PCF8531_4
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Product data sheet
Rev. 04 -- 13 June 2008
34 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
15. Application information
15.1 Typical system configuration
VLCD
VDD1 to VDD3 VDD(I2C) 128 column drivers 34 row drivers
Rpu Rpu
HOST MICROPROCESSOR/ MICROCONTROLLER SDA
PCF8531
SDACK
LCD PANEL
VSS RES SCL SDA VSS1, VSS2
VSS1, VSS2
ENR
SCL
SA0
RES
mgs483
Fig 28. Typical system configuration
The host microprocessor/microcontroller and the PCF8531 are both connected to the I2C-bus. The SDA and SCL lines must be connected to the positive power supply via pull-up resistors. The internal oscillator requires no external components. The appropriate intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and suitable capacitors for decoupling VLCD and VDD.
PCF8531_4
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Product data sheet
Rev. 04 -- 13 June 2008
35 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
15.2 Chip-on-glass application
DISPLAY 34 x 128 PIXELS
17
128
17
PCF8531
R I/O
Rsupply
3
Cext VSS1 VSS2
I/O
VDD1 to VDD3
VLCD
mgs484
Fig 29. Chip-on-glass application
The required minimum values for the external capacitors in a chip-on-glass application are:
* Cext = 100 nF between VLCD and VSS1, VSS2; Cext = 470 nF between VDD1, VDD2, VDD3
and VSS1, VSS2.
* Higher capacitor values are recommended for ripple reduction. * For COG applications, the recommended ITO track resistance must be minimized for
the I/O and supply connections. Optimized values for these tracks are below 50 for the supply (Rsupply) and below 100 for the I/O connections (RI/O). NXP strongly recommended implementing a series input resistance in the reset line (recommended minimum value 8 k) on the glass (ITO). If the reset input is not used, this input must be connected to VDD1 using a short connection.
* To reduce the sensitivity of the reset to ESD/EMC disturbances for a COG application,
PCF8531_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
36 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
15.3 Programming example
Table 17. Step 1 2 3 Programming example for PCF8531 Serial bus byte DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 SA0 0 0 0 0 1 start; slave address; R/W = 0 control byte; Co = 1; RS = 0 H[1:0] independent command; select function and RAM command page (H[1:0] = 00) control byte; Co = 1; RS = 0 function and RAM command page PD = 0 and V = 1 control byte; Co = 1; RS = 0 function and RAM command page select display setting command page H[1:0] = 01 control byte; Co = 1; RS = 0 display setting command page; set normal mode (D = 1; IM = 0 and E = 0) control byte; Co = 1; RS = 0 select multiplex rate 1:34 control byte; Co = 1; RS = 0 H[2:0] independent command; select function and RAM command page H[1:0] = 00 control byte; Co = 1; RS = 0 function and RAM command page; select HV-gen command page H[1:0] = 10 control byte; Co = 1; RS = 0 HV-gen command page; select voltage multiplication factor 5 S[1:0] = 11 control byte; Co = 1; RS = 0 HV-gen command page; select temperature coefficient 2 TC[2:0] = 010 control byte; Co = 1; RS = 0 HV-gen command page; select high VLCD programming range (PRS = 1); voltage multiplier off (HVE = 1) control byte; Co = 1; RS = 0 Display Operation
4 5 6 7
1 0 1 0
0 0 0 0
0 1 0 0
0 0 0 0
0 0 0 1
0 0 0 0
0 1 0 0
0 0 0 1
8 9
1 0
0 0
0 0
0 0
0 1
0 1
0 0
0 0
10 11 12 13
1 0 1 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 1 0 0
0 0 0 0
0 1 0 1
14 15
1 0
0 0
0 0
0 0
0 1
0 0
0 1
0 0
16 17
1 0
0 0
0 0
0 0
0 1
0 0
0 1
0 1
18 19
1 0
0 0
0 1
0 0
0 0
0 0
0 1
0 0
20 21
1 0
0 0
0 0
0 0
0 0
0 1
0 1
0 1
22
1
0
0
0
0
0
0
0
PCF8531_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
37 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
Table 17. Step 23
Programming example for PCF8531 ...continued Serial bus byte DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 0 0 0 0 0 HV-gen command page; set VLCD = 7.71 V; VOP[6:0] = 0100000 control byte; Co = 0; RS = 1 data write; Y and X are initialized to 0 by default, so they are not set here
mgs405
Display
Operation
24 25
0 0
1 0
0 0
0 1
0 1
0 1
0 1
0 1
26
0
0
0
0
0
1
0
1
data write
mgs406
27
0
0
0
0
0
1
1
1
data write
mgs407
28
0
0
0
0
0
0
0
0
data write
mgs407
29
0
0
0
1
1
1
1
1
data write
mgs409
30
0
0
0
0
0
1
0
0
data write
mgs410
31
0
0
0
1
1
1
1
1
data write; last data and stop transmission
mgs411
32
0
1
1
1
1
0
SA0
0
repeated start; slave address; R/W = 0
mgs411
PCF8531_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
38 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
Table 17. Step 33
Programming example for PCF8531 ...continued Serial bus byte DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 Display Operation
mgs411
34
0
0
0
0
0
0
0
1
H[1:0] independent command; select function and RAM command page H[1:0] = 00 control byte; Co = 1; RS = 0 function and RAM command page; select display setting command page H[1:0] = 01
mgs411
35 36
1 0
0 0
0 0
0 0
0 1
0 0
0 0
0 1
37 38
1 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
control byte; Co = 1; RS = 0 H[1:0] independent command; select function and RAM command page H[1:0] = 00 control byte; Co = 1; RS = 0 display control; set inverse video mode (D = 1; E = 1 and IM = 0)
mgs412
39 40
1 0
0 0
0 0
0 0
0 1
0 1
0 0
0 1
41
1
0
0
0
0
0
0
0
control byte; Co = 1; RS = 0
mgs412
42
1
0
0
0
0
0
0
0
set X address of RAM; set address to `0000000'
mgs412
43
0
1
0
0
0
0
0
0
control byte; Co = 0; RS = 1
mgs412
44
0
0
0
0
0
0
0
0
data write
mgs414
PCF8531_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
39 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
16. Package outline
Not applicable.
17. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5.
18. Packing information
Table 18. Symbol A B C D E F x y Tray dimensions (see Figure 30) Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction number of pockets, x direction number of pockets, y direction Value 13.72 mm 4.17 mm 12.34 mm 2.05 mm 50.8 mm 50.8 mm 3 10
x
A
C
y D
B F
E
mgs488
Fig 30. Tray details
PCF8531_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
40 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram (Figure 2) for the orientating and position of the type name on the die surface.
Fig 31. Tray alignment
19. Abbreviations
Table 19. Acronym CDM CMOS COG DDRAM EMC ESD HBM IC ITO LCD LSB MM MPU RAM Abbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Chip-On-Glass Double Data Random Access Memory ElectroMagnetic Compatibility ElectroStatic Discharge Human Body Model Integrated Circuit Indium Tin Oxide Liquid Crystal Display Least Significant Bit Machine Model MicroProcessor Unit Random Access Memory
PCF8531_4
Product data sheet
Rev. 04 -- 13 June 2008
PCF8531
mgs489
(c) NXP B.V. 2008. All rights reserved.
41 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
20. Revision history
Table 20. Revision history Release date 20080613 Data sheet status Product data sheet Change notice Supersedes PCF8531_3 Document ID PCF8531_4 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 4: Fab 1 and Fab 2 details added Product data sheet Product data sheet Product data sheet PCF8531_2 PCF8531_SDS_1 -
PCF8531_3 PCF8531_2 PCF8531_SDS_1
20000211 19990810 19990322
PCF8531_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
42 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
21. Legal information
21.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
21.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
22. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF8531_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 13 June 2008
43 of 44
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
23. Contents
General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . 13 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 13 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Display data RAM . . . . . . . . . . . . . . . . . . . . . . 13 Timing generator. . . . . . . . . . . . . . . . . . . . . . . 13 Address counter . . . . . . . . . . . . . . . . . . . . . . . 13 Display address counter . . . . . . . . . . . . . . . . . 13 Command decoder . . . . . . . . . . . . . . . . . . . . . 13 Bias voltage generator . . . . . . . . . . . . . . . . . . 13 VLCD generator . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Column driver outputs. . . . . . . . . . . . . . . . . . . 14 Row driver outputs . . . . . . . . . . . . . . . . . . . . . 14 LCD waveforms and DDRAM to data mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2 Function set . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2.1 PD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.3 Set Y address . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.4 Set X address . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.5 Set multiplex rate . . . . . . . . . . . . . . . . . . . . . . 20 9.6 Display control (D, E and IM) . . . . . . . . . . . . . 20 9.7 Set bias system . . . . . . . . . . . . . . . . . . . . . . . 20 9.8 LCD bias voltage . . . . . . . . . . . . . . . . . . . . . . 21 9.9 Set VLCD value . . . . . . . . . . . . . . . . . . . . . . . . 21 9.10 Voltage multiplier control S[1:0] . . . . . . . . . . . 22 9.11 Temperature compensation . . . . . . . . . . . . . . 22 10 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 25 11 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 26 11.1 Characteristics of the I2C-bus . . . . . . . . . . . . . 26 11.1.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11.1.2 START and STOP conditions . . . . . . . . . . . . . 26 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 8 11.1.3 11.1.4 11.2 11.3 12 13 14 15 15.1 15.2 15.3 16 17 18 19 20 21 21.1 21.2 21.3 21.4 22 23 System configuration . . . . . . . . . . . . . . . . . . . Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . Command decoder. . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Typical system configuration . . . . . . . . . . . . . Chip-on-glass application. . . . . . . . . . . . . . . . Programming example . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 27 28 29 30 30 32 35 35 36 37 40 40 40 41 42 43 43 43 43 43 43 44
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 June 2008 Document identifier: PCF8531_4

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